This invention relates to a semiconductor integrated circuit, and concerns a technique which is effective for use in a semiconductor integrated circuit comprising a decoder circuit, for example, a semiconductor memory.
In a semiconductor memory such as RAM (random access memory) or ROM (read only memory), an address decoder which forms select signals for selecting memory cells is provided. The address decoder receives address signals of, e.g., n bits and forms one select signal in accordance with 2.sup.n combinations of the address signals. By way of example, such an address decoder can be constructed of a plurality of unit decoders each of which comprises a NOR gate circuit and a NAND gate circuit. Here, in a case where such gate circuits are constructed of driving MOSFETs and load means or precharging MOSFETs, each gate circuit requires (n+1) MOSFETs. On the other hand, in a case where each gate circuit is constructed of a CMOS circuit composed of P-channel MOSFETs and N-channel MOSFETs, as many MOSFETs as 2n are required per gate circuit. In this manner, in the case of employing the logic gate circuit, the large number of elements are needed. This has now become a serious obstacle to attaining a higher integration density and a larger memory capacity of the semiconductor memory.
It is therefore considered that the number of elements is reduced by utilizing a switch tree decode construction. In the switch tree decode construction, however, the number of MOSFETs increases as the branch of a tree spreads, and whereas smaller numbers of MOSFETs are arranged near the base point of the tree, the number of MOSFETs to be disposed on the distal end side of the tree is enlarged in the extreme case. Accordingly, the gates of the large number of MOSFETs are connected in common to an input signal line for the MOSFETs on the distal end side. As a result, input gate capacitances and parasitic capacitances of large capacitance values are coupled to the input signal line. Such undesired capacitances retard the change of the input signal of the MOSFET on the distal end side, in other words, they retard the switching operation of the MOSFET, so that a higher speed operation cannot be achieved.
Regarding the address decoder of a dynamic RAM, refer to, for example, the official gazette of Japanese Patent Application Laid-open No. 53-41946.